1. Field of the Invention
The present invention relates to controllers and, more particularly, to graphics controllers used with computer systems.
2. Description of the Related Art
Computer systems conventionally use graphics controller chips to provide high resolution graphics. Graphical controller chips are special purpose processing units that are designed to draw graphics, such as render two-dimensional or three-dimensional shapes, with high performance on a display device. These graphics controller chips are also referred to as graphic accelerators.
Graphics controller chips typically include a local memory, namely Random-Access Memory (RAM), that is used by the graphics controller in producing the complex graphics. For example, a graphics controller typically includes a graphics engine that makes use of the local memory to produce complex graphics. The local memory also acts in part as a frame buffer because it is used to store a frame of image data to be displayed on the display device. Periodically, the displayed images on the display device are refreshed to provide persistence to the images being displayed on the display device. The refresh operation is performed by accessing the image data stored in the frame buffer provided by the local memory. External components of a computer system (e.g., microprocessor) may also stream data into or out of the local memory.
Thus, given the various resources competing for use of the local memory, conventional graphic controller designs normally operate an interface to the local memory at its maximum speed so that the bandwidth with respect to the local memory is maximized. However, in doing so, the power consumption of the electrical circuitry associated with the memory interface is very high. In other words, the speed (or frequency) at which the memory interface is operated determines its power utilization. Thus, conventional approaches have been able to provide fast access to the memory but do so at the expense of wasting significant amounts of power. Efficient use of power is today an important goal for all computer systems, particularly for portable computers when operating on battery power.
Thus, given the ever increasing sensitivity towards power consumption of computer systems, there is a need to manage the power-consumption of graphics controllers.
Broadly speaking, the invention relates to a controller (or controller chip) that provides reduced power consumption without impacting performance. The controller monitors activity of components within the controller which require access to a local memory, and then decreases a clocking frequency for a memory interface to the local memory when the monitoring indicates that reduced amounts of activity are present. Following such a decrease in the clocking frequency, when increased amounts of activity are detected, the clocking frequency is increased for high performance operation. The controller thus tailors the clocking frequency for the memory interface in accordance with the amount of activity of these components that require access to the local memory so that overall less power is used by the controller yet the performance is essentially not hindered. The invention is particularly well suited for use with graphics controllers, as such controllers require access to local memories.
The invention can be implemented in numerous ways, including as a system, a device, an apparatus, and a method. Several embodiments of the invention are summarized below.
As a method for managing power consumption of a graphics controller having an interface to a local memory, one embodiment of the invention includes the acts of: determining a bandwidth load on the local memory; and providing a clock to the interface, the clock having a frequency dependent upon the bandwidth load, and the interface providing access to the local memory at a rate determined by the frequency of the clock. Preferably, the method reduces power consumption by the graphics controller by reducing the frequency of the clock when the bandwidth load decreases, and then rapidly increasing the frequency of the clock as the bandwidth load increases.
As a method for managing power consumption of a controller having a local memory associated therewith, one embodiment of the invention includes the acts of: receiving status information indicating local memory usage requirements for the local memory of the controller; determining whether the usage requirements are below a threshold condition; and operating the graphics controller to interact with the local memory in accordance with a regular frequency clock when the usage requirements exceed the threshold condition or in accordance with a reduced frequency clock when the local memory usage requirements are below the threshold condition. When the reduced frequency clock is used by the controller, power consumption of the graphics controller is substantially lowered as compared to the power consumption of the controller when the regular frequency clock is used.
As a graphics controller for use with a computer system including a processor, a system bus and a display device, one embodiment of the invention includes: a system bus interface for coupling to the system bus of the computer system; a local memory; a local memory interface coupled to the local memory, the local memory interface controls access to the local memory; a display interface for coupling to the display device of the computer system; an arbitration unit coupled to the system bus interface, the local memory interface, and the display interface, the arbitration unit operates to arbitrate access to the local memory via the local memory interface; and a clock controller operatively connected to at least one of the local memory interface and the local memory, the clock controller producing a first clock for use by the at least one of the local memory interface and the local memory.
As a graphics controller for use with a computer system including a processor, a system bus and a display device, another embodiment of the invention includes: a system bus interface for coupling to the system bus of the computer system; a local memory; a local memory interface coupled to the local memory, the local memory interface controls access to the local memory; a display interface for coupling to the display device of the computer system; a graphics engine operatively connected to the local memory interface, the graphics engine renders complex images to be displayed on the display device; means for monitoring activity of at least one of the system bus interface and the graphics engine to produce a memory access load indication; and means for producing a memory clock signal for use by at least one of the local memory interface and the local memory, the memory clock signal having a frequency that varies depending upon the memory access load indication, wherein the frequency is lower when the memory access load indication indicates a lack of or reduction in activity.
The advantages of the invention are numerous. Different embodiments or implementations may have one or more of the following advantages. One advantage of the invention is that controllers can operate with substantial power savings while still providing high performance. Another advantage of the invention is that computer systems, particularly battery-powered computer systems, overall consume less power when the controller according to the invention is utilized. Hence, with battery-powered computer systems, battery lifetime (before needing to be recharged) is extended by the invention.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.